Analog-to-digital and digital-to-analog converters have been described in the past utilizing a simple solution that is based on the periodic charging and discharging of a capacitor. These are sometimes referred to as Shannon-Rack decoders. These types of decoders employ a constant current source that is utilized to charge a capacitor through a switch. For the digital-to-analog conversion, the output on the capacitor, after a number of switching cycles, represents the analog value. A clock is necessary to synchronize the operation of the decoder in conjunction with the binary input. A weighting factor is provided during each interval of time that the capacitor is charged and discharged to ensure that the capacitor voltage is halved each half-period through discharging. Due to practical problems such as timing and the need of high precision and low-drift components, as well as a serial digital input, such a converter has never been widely utilized.
A modern version of the concept of charge weighting used in the Shannon-Rack decoder which is tailored for monolithic integration is the concept of a charge redistribution decoder. In this decoder, intermediate results are stored dynamically with minimum losses on high-precision capacitors (e.g., MOS capacitors), and are moved from one capacitor to another by MOSFET switches. One of the more widely utilized charge redistribution converter techniques is based on successive approximation. This technique primarily utilizes capacitors having binary weighted values with the top plate of all the capacitors connected to one input of a comparator and the bottom plate switched between various voltages. The steering of the various switches is controlled by the comparator through auxiliary logic circuitry.
The conversion process is essentially performed in three steps, a sampling step, a hold step and a redistribution step. In the sampling step, the top plates of the capacitors are normally connected to ground, or some suitable sample reference voltage, and the bottom plates to the input voltage. This results in a stored voltage on the bottom plate which is proportional to the input voltage. In the hold step, the top plate is electrically isolated and the bottom plates are normally connected to ground or some suitable hold reference voltage. Since the charge on the top plate is conserved, its potential goes to the negative of the input voltage. In the conversion or "redistribution" step, each individual bit is tested by sequentially connecting the bottom plate of each of the capacitors to either a redistribution reference voltage or to ground until the voltage on the top plate reaches a predetermined voltage. This is usually the trip point of the comparator.
One disadvantage of a charge redistribution converter is incurred when sampling positive and negative signals. Typically, during the hold or reset step, all of the bottom plates of the capacitors are set to a predetermined hold reference voltage, such as ground. This results in the top plates being pulled above or below the trip point of the comparator. For example, if the hold reference voltage is equal to zero volts or ground and only a single unipolar redistribution reference V.sub.R is available for the bottom plate switching during the redistribution step, the top plate can be pulled positive only toward V.sub.R, and only positive input signals can be converted. This is true for any array that utilizes only two levels (i.e., a unipolar reference and ground) wherein the top plates are preset to one of the other during the hold or reset step. A problem arises when a negative voltage is sampled, resulting in a positive voltage on the top plates in the hold step, which requires a negative redistribution reference voltage during redistribution. Therefore, a bipolar reference voltage is required when sampling a bipolar input signal.
This disadvantage can be cured by setting half the array to either V.sub.R or zero and setting the other half of the array to the other of the two levels. However, one disadvantage to this technique is that the capacitor associated with the most significant bit (MSB) is equal to half the capacitance of the array. Testing of this bit occurs for analog values around zero. If the capacitor is not equal to exactly one-half the total capacitance of the array, a significant differential nonlinearity can be incurred. This is not a problem for A/D converters of the order of three bits, but this can be a problem for A/D converters of ten bits or higher. Generally, the MSB capacitor of an N-bit array must equal half the total capacitance within one part in 2.sup.N to avoid the differential non-linearity. This conversion error occurs because the major bit transition occurs at zero signal. Therefore, a need exists for an A/D converter that utilizes ground and a unipolar reference and can redistribute the charge in the capacitor array without requiring a major bit transition to be at the zero signal level. The errors caused by the MSB capacitor size then occur at a larger input signal and are thus a small fraction of that signal.